Circuit arrangement for testing a digital circuit

摘要

The invention relates to a circuit arrangement for the dynamic real-time test of a synchronous digital circuit (device under test) with m inputs and n outputs, with a pulse sequence generator which contains a clocked shift register which can be provided with feedback and the data input of which can be blocked and which generator supplies the pulse sequences for testing the digital circuit, and is characterised by the fact that a shift register of at least m stages is used for converting serial operational input data into parallel operational input data for the digital circuit, the n parallel outputs of the shift register being connected to the m data inputs of the digital circuit, and that a mode switch is provided by means of which it is possible to switch from the normal operation of the digital circuit to a test mode in that the serial data input of the shift register is separated from the serial data input of the digital circuit and is connected to the output of a feedback branch. The advantage of this circuit arrangement lies in the fact that it is possible to switch to a test mode without great additional complexity and, at the same time, a test loop is automatically run. <IMAGE>