| 摘要 |
PURPOSE:To enable to easily perform wirings for the titled integrated circuit without needing a useless area by a method wherein the width directions of the gates of the FETs of all input and output buffer circuits are set in parallel with one another, and also, all of the input and output buffer circuits are respectively formed into a regular square-shaped pattern. CONSTITUTION:Driver EFETs Q21 and Q22 shaped as if a driver EFET was divided into two pieces are connected in parallel with each other. 611 is used as a drain electrode for a load DFETQ1 and 621 is used as a gate electrode for the load DFETQ1. A drain electrode 612 for the Q21 combined with a source for the FETQ1 is connected at the equal potential as that of a drain electrode 614 for the Q22. When these patterns are overlapped three pieces one over another in such a way that the long sides thereof come in contact with one another, the entire shape becomes nearly regular square. |
