| 摘要 |
PURPOSE:To eliminate the need for minute control of delay of a gate or load capacitance by forming a reset pulse having a period of pulse width of an input signal by means of a D-FF without requiring resetting of plural FF circuits at the same time. CONSTITUTION:A decoder 25 detects the state just before a leading edge of the 1st input signal (figure A) frequency-divided by 1/m to generate an output of H. This is similarly applied to a decoder 26 also. Only the leading edge of the frequency-divided input signal is noted, and the input signal set earlier receives the priority in the state being neither UP nor DOWN state with (-UP=H and -DN=H) to bring the state to the UP or the DN state. In the case of the state in figure A or figure B, for example, an output of the decoder 25 is fed to the D-FF27. This output is sampled by the 1st pulse signal and a pulse -TUP in figure C is generated from the FF27 and also the said output is fed to a D-FF28 and a pulse -CDN in figure D is generated. An RS-FF is set by the output -TUP and the output signal -UP falls down to L level as shown in figure G. |
