| 摘要 |
PURPOSE:To produce a stable output despite an input timing from an input means by inputting as signals sample-held at the end of a clock pulse the U/D signals to be inputted in the U/D input terminal of an up/down counter (U/D counter). CONSTITUTION:When a switch 4 is turned on at the time of t1, the first clock pulse (d) outputted by a clock pulse generator 14 is inputted in a D-F.F12 as a signal (f). The second clock pulse (c) is inputted in the clock input terminal C of the D-F.F12, and the start-up timing holds a signal (f) level to output as a signal (g). While the output signal (i) from a D-F.F11 is made by holding the output signal (h) level from the F.F10 by using a signal (j) start-up as a clock input. When the signal (g) starts up at the time of t3, the U/D counter 1 is counted up and an output voltage V0 of a D/A converter rises by one step. Because the U/D signal input of the U/D counter 1 and a clock input are not inputted together, a stable output voltage can be obtained. |
