| 摘要 |
<p>The conversion of bit-interleaved to byte-interleaved data is achieved using a memory (11) and a universal shift register (14). The period of each bit-interleaved timeslot is divided into three parts for which corresponding timing signals are provided. During the first timing signal, the content of a memory location corresponding to an output channel is loaded into the universal shift register (14). During the second timing signal, the incoming bit associated with the timeslot is shifted serially into the register (14) and during the third signal, the content of the register (14) is returned to its original location in the memory (11). After a frame of bit-interleaved data has been received at the register (14), the memory (11) contains the corresponding frame of byte-interleaved data.</p> |
