发明名称 PARALLEL PROCESSING SYSTEM OF RECURRENT PROCEDURE INCLUDING INDIRECT ADDRESSING
摘要 PURPOSE:To attain the parallel processing of a recurrent procedure and to increase the processing speed, by providing a means which avoids a memory conflict that is possibly caused by the indirect addressing. CONSTITUTION:An indirect address calculating part 2 produces an indirect address L(i) from an index (i) generated by an index generating part 1 and then gives an access to a memory 7 to read out the data A[L(i)] and B(i). Both data A and B are added together by a pipeline adder 8, and an SUM is delivered. While the presence or absence of a conflict is controlled for each address L(i) of the memory 7 by a conflict detecting 3 and a conflict table 4. Then an access state display M[L(i)] is delivered when an access is given to the address L(i). A display M is used for controlling a gate 9, and the SUM output is inhibited in a conflict mode. This avoid a conflict and can perform the parallel processing of a recurrent procedure. Thus the processing speed is increased.
申请公布号 JPS60150138(A) 申请公布日期 1985.08.07
申请号 JP19840004758 申请日期 1984.01.17
申请人 KOGYO GIJUTSUIN (JAPAN) 发明人 IKEDA MASAYUKI
分类号 G06F9/38;G01N15/00;G06F7/00;G06F9/35;G06F17/18 主分类号 G06F9/38
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