发明名称 FAULT DETECTOR FOR TERMINAL CONTROL PROCESSOR OF ELECTRONIC EXCHANGE
摘要 PURPOSE:To improve the fault detecting sensitivity as well as the processing efficiency by dividing a terminal control processor into two blocks and monitoring the presence or absence of an access and the length of this access to a shared memory between both processors by these processors to each other. CONSTITUTION:Control processors 7 divided into two parts via a control bus 8 are connected to an exchange control processor 6 of a system. These processors 7 are connected to terminal control processors 9 via a reset circuit 12 and a memory controller 13 respectively. Then each of divided terminals 11 are connected to the processors 9, and common memory devices 10 are connected to the controllers 13 respectively. When the controllers 13 deliver the requests to processors 7 and 9 for use of the devices 10, the faults of both processors 7 and 9 are detected with each other by the output of controllers 13 in response to the requests of the controllers 13. Then the circuit 12 is reset based on the result of the fault detection. This improves the fault detecting sensitivity and facilitates an easy increase of terminals 11.
申请公布号 JPS60149251(A) 申请公布日期 1985.08.06
申请号 JP19840005035 申请日期 1984.01.13
申请人 MATSUSHITA DENKI SANGYO KK 发明人 FUJITA HIROSHI
分类号 H04Q3/545;H04M3/24;H04M3/26 主分类号 H04Q3/545
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