| 摘要 |
PURPOSE:To optimize both the Schottky withstand voltage of a gate and the contact resistance of an electrode by a method wherein the carrier concentration is reduced in proximity to the suface in the neighborhood of the gate electrode, and increased in proximity to the surface immediately under the source and drain electrodes. CONSTITUTION:The ion implantation for an N type active layer 3 is performed to a semi-insulation GaAs substrate 1, and next N<+> ions are implanted 4 except the gate section. At this time, the surface carrier concentration is decreased by Si ion implantation in order to increase the withstand voltage of the gate electrode 2. Then, the ion implantation for a shallow N<+> layer 41 is performed at a distance from the gate section. Thereafter, a source-drain metal is formed outside the layer 41 and made as an ohmic electrode 5. Further, the gate electrode 2 is formed so as to cover the entire surface. At this time, the electrode 2 contacts the layer 4, but the layer 4 has a low surface concentration and therefore has no deterioration in gate withstand voltage. On the other hand, since the layer 41 is formed immediately under the electrode 5, the source-drain electrodes 5 do not show the deterioration in contact resistance. |
