| 摘要 |
A signal analyzing circuit for a periodically occurring signal such as from a video signal source (VSS). The circuit comprises a store (m) having separate store locations m associated with corresponding regions defined as rows and columns of a picture display of the periodically occurring video signal. In addition, a time signal generator (TG) is provided for the synchronous control of the video signal source (VSS) and the store (m). For filling in a simple manner, without disturbance, the store locations (m) with the mean value of the video signal taken per accurately determined region, the output of the signal source (VSS) is coupled via an analog-to-digital converter (A/D) to counting inputs of a number of counters (BC1 to BC7) equal to the number of regions per row. The counters are operative sequentially and periodically. Each counter (BC1 to BC7) is followed by a buffer register (BR1 to BR7) receiving the counting information in the line blanking period at the end of the last signal period in the row of regions and the counter (BC) is subsequently reset. The buffer register (BR) is followed by the store (m) with the separate store locations (m), which are filled with the previous counting information during the next counting operation.
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