| 摘要 |
PURPOSE:To prevent the generation of a data error by controlling the length of a strap bit of the asychronous data when the parallel data is demodulated to the asynchronous data and then controlling the speed of the asynchronous data. CONSTITUTION:The asynhronous parallel data 2 supplied from a transmission line is given to a data demodulating part 4, and a count start signal 5 is changed to L when a start bit is delivered. Thus it is impossible to obtain an AND between a reference clock and the signal 5, and the counting is carried out by the sample clock signal given from an OR circuit 8. The output of a counting circuit 6 is supplied to a comparator circuit 7 to be compared with an output period deciding signal controlled previously. Then an output pulse 7 is sent to the part 4 and the circuit 6 via the circuit 8. Therefore the sampling clock of the input at one side of the circuit 8 is applied forcibly to control the length of a stop bit. This prevents the generation of a data error. |
