| 摘要 |
<p>PURPOSE:To reduce power consumption while a power supply is kept off by discontinuing the working of a central airthmetic processor after detecting an OFF state of a power supply switch and at the same time setting an address decoder under an inactive state. CONSTITUTION:An address decoder 2 and memories 3-6 are connected to a central arithmetic processor 1 via an address bus AD1, etc. The ON and OFF terminals of a power supply switch SW1 are connected to an earth and a +B power supply respectively. Then the SW1 is connected to a reset terminal IN1, etc. of the device 1 through each juncture of a resistance R1 and a capacitor C1. Furthermore, the SW1 secures a connection between a system OFF output terminal OUT of the device 1 and an action control terminal of the decoder 2 via a buffer 8, a resistance R2, a capacitor C2 and a buffer 9. Thus an OFF state of the SW1 is detected to stop the working of the device 1. At the same time, a system OFF signal is delivered. Thus the decoder 2 is inactivated after a prescribed period of time set by a time constant of the R2 and the C2.</p> |
