| 摘要 |
PURPOSE:To attain simply and quickly the transfer of data by using a common RAM as a common data area together with a status control circuit and a common RAM control part. CONSTITUTION:A CPU1a sets both SET and STATUS signals at ''1'' when a signal ST is ''0''. Then a signal GATE is set at ''1'' to give an access to a common RAM5, and the data is written or read. The CPU1a sets the signal STATUS at ''0'' after an access. A CPU1b sets the signal GATE at ''1'' when signals ST and STATUS are set ''1'' and ''0'' respectively and gives an access to the RAM5 to read or write the data. Then the CPU1b sets the signal SET at ''1'' and the signal ST at ''0'' after an access and shifts the RAM5 to the CPU1a. |
