| 摘要 |
PURPOSE:To enhance performance in vector operational processing by making it possible for a vector register to specify plural addresses or by allowing plural number of reading and writing. CONSTITUTION:Plural registers VR0-VR255 consist of plural elements, which are sequentially accessed by 0-3 units of banks, and data processing is executed. In this case, a range of elements are mated to the order of the bank as shown in the figure so as to be arranged, and banks 0-3 are composed of elements with the same order at every register. With sequential access to these elements data processing is executed. These banks 0-3 are caused to be possible to read plural different elements, read/write them or write in plural different elements. |
