发明名称 MESSAGE TRANSFER BUFFER SYSTEM
摘要 PURPOSE:To prevent the load of a control section and the capacity of a buffer and a memory from being increased by transmitting/receiving a signal while code number is counted and applying prescribed processing when the number reaches a designated code number so as to quicken the effective transfer speed. CONSTITUTION:A counter circuit CTR counts the code number and acts like the counter circuit of an address of a buffer MB, and designates an address via a buffer control circuit MBC and outputs the result of count to a comparator circuit CMP. The comparator circuit CMP compares the result of count with a numeral commanded by the control section CPU in advance and when they are coincident, the result is informed to the control section CPU via a control bus (c). The information is transmitted by the control of the control circuit CPU.
申请公布号 JPS60145748(A) 申请公布日期 1985.08.01
申请号 JP19840001041 申请日期 1984.01.07
申请人 FUJITSU KK 发明人 KATOU MASABUMI;KATSUYAMA TSUNEO;KAMOI EDAMASU
分类号 H04N1/00;H04L12/54 主分类号 H04N1/00
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