发明名称 TESTING METHOD OF EMITTER-CONNECTED LOGIC GATE
摘要 PURPOSE:To facilitate the identification of the quality of transistors composing an input/output section of an emitter-connected logic gate by using a pattern of a voltage/current characteristic generated with the application of a test signal. CONSTITUTION:At the first step, a switch section 13a is turned ON (with the power source positive pole supply terminal Vcc set to the earth potential) by control with a control section 10 while switching sections 13b and 13c turned OFF (with a negative pole terminal VEE and an auxiliary power source supply terminal VT opened) and a test signal is applied to the connection of ICs 20a and 20b on a printed board 2 from a prober 14 from a test signal generating section 11 to obtain a voltage/current characteristic at a display output section 12b. Then, at the second step, with a switch 13b ON and the other OFF, the test signal is applied. At the third step, with a switch 13c ON and the other OFF, the test signal is applied. Thus, the use of the pattern of the voltage/current characteristics thus obtained at the first to third steps facilitate the identification of the quality of transistors composing an input/output section of a emitter-connected logic gate.
申请公布号 JPS60146162(A) 申请公布日期 1985.08.01
申请号 JP19840002202 申请日期 1984.01.10
申请人 FUJITSU KK 发明人 SERIZAWA TSUGUHITO
分类号 G01R31/28;G01R31/317 主分类号 G01R31/28
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