CIRCUIT FOR GENERATING A DELTA VALUE

摘要

A delta value generating circuit in an adaptive delta codec, comprising a delta value register, a control terminal for indicating increase or decrease of the delta value and adder/subtractor for increasing or decreasing the delta value in the register in accordance with a level at the control terminal. The adder/subtractor has first input terminals connected to the output terminals of the register and second input terminals connected to a predetermined number of upper bits of the output terminals of the register and the control terminal in accordance with a level at the control terminal.