| 摘要 |
PURPOSE:To obtain the master slice LSI capable of effective reduction in chip area by a method wherein the structure for wiring is formed of cubic multilayers, and wiring regions are provided on basic cells. CONSTITUTION:As the first layer wiring, basic cells 100, 200, and 300 each consisting of N-channel transistors 101, 201, 301 and P-channel transistors 101, 202, 302 are wired as lines W1. As the second layer wiring, terminals C3 are wired as lines W2; as the third layer wiring, wiring is performed as lines W3. Points C4 are parts of through-hole contact formation to connect the second layer wirings W2 to the third layer wirings W3. Thereby, the region necessary only for wiring is a region WE1 in the LSI, and a region WE2 on the basic cell column serves as the substantial wiring region. |
