| 摘要 |
An adder circuit in an arrangement in which two binary numbers consisting of n bit positions, addend and augend, and one possible input carry bit each are logically combined in order to generate a sum S1...Sn consisting of n bit positions and an output carry bit, all bits of the addend Al and of the augend Bi and the input carrier bit in each case being supplied in such a manner that from these inputs, the sum bits Si and the output carry bit Cn + 1 are in each case generated independently of one another, in parallel and simultaneously by n + 1 logically isolated combinatorial networks, the logical networks for the sum bits Si being defined by the formula: Si = A1(+)Bi [(Ai-1+Bi-1)[Ai-2+Bi-2)[...[(Al+Bl )C+AlBl]+...]+Ai-2Bi-2]+Ai-1Bi-1 and the output carry bit being defined by: Cn+1 = (An +Bn)C'n +AnBn for the complementary adder and by: C'n+1 = (An +Bn)C'n +AnBn for the direct adder. <IMAGE>
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