发明名称 MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To improve the throughput of the whole system by providing an extra signal line between an arithmetic processor and an input/output processor and using its signal to operate a program which prevents a confliction between a data and an address path. CONSTITUTION:The input/output processor 4 checks an input/output part memory use signal 21 when entering a memory use period 201 and if a memory is being used by the arithmetic processor 5, the processor 4 holds itself until an arithmetic period 210 and then enters the memory use period 201. The arithmetic processor 5, on the other hand, checks a signal 20 when entering a memory use period 211 and if the input/output processor 4 is in the memory use period 201, the processor 5 holds itself until an input/output period 200 and then outputs the signal 21 to enter the memory use period 211. The program for said operation is generated previously and programs for the input/output processor and arithmetic processors are generated individually; and then the former program is only inserted into both the latter programs where there is a memory use instruction to perform efficient processing without any bus contention.
申请公布号 JPS61177565(A) 申请公布日期 1986.08.09
申请号 JP19850018617 申请日期 1985.02.04
申请人 NEC CORP 发明人 SASAKI KEITA
分类号 G06F12/00;G06F9/52;G06F13/16;G06F13/38;G06F15/16;G06F15/177 主分类号 G06F12/00
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