发明名称
摘要 <p>PURPOSE:To prevent the malfunction and to reduce the power consumption, by providing a control means which stops and restarts the supply of the clock signal plus a control means which stabilizes the restarting of the clock signal to a processor processing a clock oscillating circuit which uses a quartz oscillator. CONSTITUTION:The timing control is given to a processing part 1 by means of a clock signal 6 supplied from a clock generating part 5, and then a program is processed. The part 5 includes a clock generating circuit 11 using a quartz oscillator etc., and AND gate 25 which supplies the clock to the part 1, a supply inhibiting FF22 which inhibits the supply of clock to the part 1 through the gate 25 by an inhibition request signal 23 and for a period decided by a counter 17, and an oscillation stopping FF16 that stops the generation of clock at the circuit 11 by a stop request signal 15. Then the supply of clock to the part 1 through the gate 25 is controlled and inhibited at a control part 2 for a period decided by the counter 17 form the restart 18 of the generation of clock at the circuit 11.</p>
申请公布号 JPS6135565(B2) 申请公布日期 1986.08.13
申请号 JP19800171604 申请日期 1980.12.05
申请人 NIPPON ELECTRIC CO 发明人 ISHIHARA TOMIHIRO;MAEHASHI YUKIO
分类号 G06F1/32;G06F1/04;G06F15/78 主分类号 G06F1/32
代理机构 代理人
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