发明名称 |
MULTIPLE FREQUENCY DIGITAL PHASE LOCKED LOOP |
摘要 |
An improved multiple frequency digital phase-locked loop circuit 10 is described. The improved digital phase-locked loops utilizes a single circuit 12 to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal 30 with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of a lock detector 22 wherein the phase-locked loop can be programmed for a plurality of known operating frequencies. <IMAGE> |
申请公布号 |
AU3787785(A) |
申请公布日期 |
1985.07.30 |
申请号 |
AU19850037877 |
申请日期 |
1984.12.31 |
申请人 |
MOTOROLA, INC. |
发明人 |
LEVINE, STEVEN N. |
分类号 |
H03K5/26;H03D13/00;H03K5/00;H03K5/22;H03K23/66;H03L7/00;H03L7/06;H03L7/085;H03L7/095;H03L7/099;H04L7/033 |
主分类号 |
H03K5/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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