| 摘要 |
PURPOSE:To decrease sampling mistakes even in a data transfer at high speed for a comparatively long range by providing a delay means for giving a delay to a reception timing signal inputted from a pulse generating means at predetermined finess. CONSTITUTION:A pulse generator PG generates a transmission timing signal ST 2' and a reception timing signal RT' in phase at first. Reception data SD is delayed by a time DELTAT from a transmission timing signal ST2 and reaches a receiver as reception data RD. On the other hand, the reception timing signal RT' is inputted to delay time setting circuits DT1, DT2 via a delay circuit DL1 while being delayed in predetermined finess (e.g., in the unit of 10+1sec). The delay time setting circuits DT1, DT2 select the input from the delay circuits DL1, DL2 so that the final reception timing signal RT is delayed by the time DELTAT from the transmission timing signal ST2. |
