| 摘要 |
<p>DATA RETENTION CIRCUIT A circuit for retention of electrically encoded data is provided that synchronizes the functions of a processor unit generating the data and a memory unit storing the data during a powerdown sequence. A voltage comparator provides a signal when power to the circuit drops below a predetermined level, and the signal actuates transfer of data from volatile Random Access Memory to non-volatile Electrically Erasable Programmable Read Only Memory. A logic gate synchronizes the functions of the voltage comparator, processor, and memory units such that data is transferred between volatile and non-volatile memory and the processor is reset only after the processor has completed the servicing of any interrupt routines it may be running at the beginning of the power-down sequence.</p> |
