| 摘要 |
Circuitry for validating the integrity of PCM data transmitted through a digital switching network is shown. The space stage of the switching system requires that appropriate data validity be maintained throughout. A parity scheme is employed to fulfill this requirement. For detection of invalid parity, an alarm notification is sent to the central processing unit (CPU) of the switching system. The CPU may then interrogate the space switching circuitry to determine the particular location of the parity failure. In addition, the circuitry provides for a testing feature, such that, the operation of the parity checking circuits may be validated.
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