发明名称 DIGITAL-TO-ANALOG CONVERTER
摘要 PURPOSE:To use a low speed clock by dividing an input into two, the upper and lower bit sides, integrating a group of a small bit number by a single current source, and integrating the other group for a reference time by using a current source selected from plural current sources. CONSTITUTION:A data DH of the upper 6-bit is preset to a high-rank counter 32a, and a data DL of the lower 10-bit is loaded to a low-rank latching circuit 34a. In accordance with ''1'' in the data DL, a current source 2<2>i0 is connected to an integral line L1 by a control signal M3. When a converting instruction comes, switches SW1, SW31 and SW32 are controlled by control signals S1, S31 and S32, respectively, and an integral operation is started, and simultaneously, down- counting of the counter 32a is started. The control signal S32 switches the switch SW32 to an input terminal T1 side only for one period of a clock signal phi, therefore, the switch SW32 is switched to a ground side when one period is ended, and an integration of the lower 10-bit is ended. Thereafter, when the counter 32a becomes all bit ''0'', the switch SW31 is switched to a ground side, and an integration of the upper 6-bit is ended.
申请公布号 JPS60144025(A) 申请公布日期 1985.07.30
申请号 JP19830246501 申请日期 1983.12.30
申请人 NIPPON GAKKI SEIZO KK 发明人 KADAKA TAKAYUKI;ISHIDA KATSUHIKO;TAKAHASHI TOSHIYUKI;OGATA TAKASHI
分类号 H03M1/82;(IPC1-7):H03M1/82 主分类号 H03M1/82
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