发明名称 VITERBI DECODER
摘要 PURPOSE:To inhibit a metric calculation to a dummy bit without increasing a circuit scale by providing a code converting part for converting an inversion and a non-inversion of a receiving code by receiving a metric calculation inhibiting signal, on a branch metric calculating circuit. CONSTITUTION:At the time of a branch metric calculation, a code is converted immediately before adding a code, dummy bits QR and -QR are set to the same value, and an equal effect to that which has inhibited a metric calculation is given. Code converting parts 767, 768 are added to a branch metric calculating part 76. The code converting part 767 converts a code so as to be I=-I only when a metric calculation inhibiting signal INH from a dummy bit inserting part is active, and outputs I and -I as they are in other case. The code converting part 768 also executes the same. The dummy bit inserting part knows an inserting position of a dummy bit, therefore, the inhibiting signal INH to be inputted to the code converting parts 767, 768 from said part can be generated easily.
申请公布号 JPS60144026(A) 申请公布日期 1985.07.30
申请号 JP19840000651 申请日期 1984.01.06
申请人 FUJITSU KK 发明人 YAMASHITA ATSUSHI;KATOU TADAYOSHI
分类号 H03M13/23;H03M13/41;(IPC1-7):H03M13/12 主分类号 H03M13/23
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