发明名称 CLOCK OSCILLATING CIRCUIT
摘要 PURPOSE:To prevent completely parasitic oscillation by inserting a resistor between an output terminal of an inverter circuit and one terminal of a parallel circuit comprising a resistor and a piezoelectric vibrator. CONSTITUTION:The parallel circuit comprising a resistor R and the piezoelectric vibrator 2 is connected to the input terminal of the inverter circuit 1, a resistor R1 is connected beween the other terminal of the parallel circuit and the output terminal of the circuit 1, the vibrator 2 is grounded via capacitors C1, C2 so as to constitute a clock oscillator. The parasitic oscillation is prevented completely even with the characteristic variation of the circuit 1 and the vibrator 2 by constituting an LPF with the resistor R1 and the capacitor C2.
申请公布号 JPS60143006(A) 申请公布日期 1985.07.29
申请号 JP19830248432 申请日期 1983.12.29
申请人 FUJITSU KK 发明人 TAHIRA MASAO
分类号 H03B5/32;H03K3/03 主分类号 H03B5/32
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