| 摘要 |
<p>PURPOSE:To prevent an output signal from having the same logic continuously by providing a counter which monitors the frequency of continuation of the same logical bit of the output signal to a transmission line encoding circuit wherein bits ''1'' and ''0'' are equal in appearance probability. CONSTITUTION:The same signal of the output signal 20 is inputted to a delay element 14 a prescribed delay time later, so the output of an exclusive OR gate 42 is ''0'' when the same logic bit continues in the output signal 20 and ''1'' when different logic bits continue. A counter 31 is reset with the output of ''1'' of the gate 42 to count outputs of ''0'', the counted value of the counter 31 indicates the continuation of bits with the same logic in the output signal 20. Therefore, when the value of the counter 31 exceeds a prescribed value, a signal of ''1'' is outputted and a gate 41 inverts the logic of a control signal (output of gate 23) to prevent the continuation of the number of bits with the same logic in the output signal 20.</p> |
