| 摘要 |
PURPOSE:To obtain a delay circuit which has low power consumption and small pattern area and obtains a large delay time by composing the circuit of one depletion type FET and two inverter circuits without using many inverter circuits. CONSTITUTION:When an input signal IN varies from H to L, the output signal c2 of the depletion type FET12 is to rise to H, but the source is held at H and the gate is held at L; and the FET does not turn off, but a current becomes difficult to flow, thereby delaying the variation of the signal c2 to H. The signal c2 rises from a source potential VDD up to a potential much lower than the threshold voltage of the FET12, so the operation speed of an inverter 13 is reduced and the delay time tpdHL of an output signal OUT is further increased. When the input signal IN varies from L to H, on the other hand, the gate of the FET12 goes up to H and the source goes down to L to make the current difficult to flow, varying the signal c2 to L smoothly. The operation speed of the inverter 13 is not reduced, so the delay time tpdLH of the output signal OUT is short. |
