发明名称 COMPUTER INTERFACE SYSTEM
摘要 PURPOSE:To execute an input/output instruction and maintenance and diagnosis of a central processing unit by connecting the central processing unit and a service processor with a single interface line and also providing a channel device to the low-order of the service processor. CONSTITUTION:A CPU1 has a CPU side interface circuit (SVA)11 and the SVA is connected to a service processor (SVP) interface line 5. An IO processor (IOP)8 is connected with the CPU1 by the interface line 5. The IOP8 has an SVP2, a channel device (CH)3 and a buffer memory (RAM)7. The SVP2 has an SVP side interface circuit (SVU)21. A device (IO)6 is connected to the CH3. Moreover, the SVP2 and the CH3 in the IOP8 are operated in time division under one processor. Thus, the input/output instruction and the maintenance/disagnosis of the CPU are executed.
申请公布号 JPS60142764(A) 申请公布日期 1985.07.27
申请号 JP19830246673 申请日期 1983.12.29
申请人 HITACHI SEISAKUSHO KK 发明人 YOSHIDA KATSUO;IKEDA KOUICHI;FUNAKUBO NOBUO
分类号 G06F13/14;G06F11/22;G06F13/12;(IPC1-7):G06F13/12 主分类号 G06F13/14
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