| 摘要 |
PURPOSE:To attain high-speed processing of various bit operations related to shift operation by using adders to select bits in the shift operation. CONSTITUTION:If a control input signal is set to 011 when three digits are to be shifted to the left, a control input signal 3 is added by respective adders 2-1-2- (n-1) and the added values are outputted to selecting circuits as selecting signals. The selecting circuit 1-1 outputs the 3rd bit of the input signal and the selecting circuit 1-2 outputs the 4th bit and a value shifted by three bits. When m digits are to be shifted to the left, m is applied to a control input signal, and when m digits are to be shifted to the right, the complement of 2 of m is applied. Delay related to the shift operation is only the operation delay of the adders and the selecting circuits, so that high-speed operation is attained.
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