发明名称 TESTING CIRCUIT
摘要 PURPOSE:To minimize the occupancy of a terminal, also to make a malfunction due to noise difficult to occur, and to execute sufficiently a test item by forming a test signal by a clock generating circuit and plural bit counters, etc. CONSTITUTION:Both a reset input signal 1 and a test input signal 2 go to ''1'', the output of a clock generating circuit 3 goes to ''0'', the reset input terminal R of a plural bit counter 4 of 2 bit, etc. goes to ''1'', thereafter, when the signal 1 goes to ''0'' and a clock input terminal CL goes to ''1'' by an output ''1'' of the circuit 3, the counter 4 is brought to increment and the output is varied. Subsequently, three kinds of 2 bit test signals except ''00'' for showing a non-test state in a 2 bit output outputted by the counter 4 are outputted. By the constitution in which said signals 1, 2 are not treated as independent ones and also plural test input signals are not combined, the occupancy of the terminal is minimized, also the probability of generation of a malfunction caused by a fact that two input signals both go to ''1'' due to noise is made small, and also various test items can be executed sufficiently.
申请公布号 JPS60142283(A) 申请公布日期 1985.07.27
申请号 JP19830251199 申请日期 1983.12.28
申请人 SUWA SEIKOSHA KK 发明人 SASAZAKI KIMIHISA
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F11/273;H03K23/50 主分类号 G01R31/28
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