发明名称 DETECTION CIRCUIT OF LINE SYNCHRONIZING CODE OF G3 FACSIMILE SIGNAL
摘要 PURPOSE:To allow detection of EOL codes at a high speed with simple constitution and to offer flexibility with respect to code length of special codes by making it possible to detect EOL codes with a special format in a code strng by processing at every word without bit handling. CONSTITUTION:A sum of the number outputted by a register 4 and that of zero its which continue from the highest order of eight-bit data of an input to the lower order are outputted at an A side of a logical operation circuit 2. The number of zero bits which continue from the lower order to the higher order is outputted at a B side. A comparator 5 inputs the value of the logical operation circuit 2 at the A side, decides whether it is beyond 11, and when it is beyond 11, the comparator 5 outputs a detection signal of an EOL code. When fourth bit of the output signal at the B side is zero, a selector 3 is controlled, and the output value at the B side is inputted to an input of the registor 4. Then addition of new continuous zero bits is started. When fourth bit of the output signal at the B side is one, the output at the A side is set to an input of the registor 4 by a selector 3.
申请公布号 JPS60141075(A) 申请公布日期 1985.07.26
申请号 JP19830247048 申请日期 1983.12.28
申请人 NIPPON DENKI KK 发明人 MOTOBAYASHI TOSHIHIKO
分类号 H04N1/36 主分类号 H04N1/36
代理机构 代理人
主权项
地址