发明名称 GATE ARRAY LSI
摘要 PURPOSE:To reduce the capacitance and the voltage drop, and to enable the titled device to be resistant to noises by reduction of the capacitances between adjacent lines and of cross-talks because of fine wires in sections of close density, by a method wherein the width of signal lines running under branching in the same direction in the same layer is made different according to the current value. CONSTITUTION:A signal line L1 runs from a gate G0 to the first branching point P1, where signal lines L2 and L3 start by two-branching. P2 and P3 represent the secondary and tertiary branching points, L4 and L5 represent the signal lines branched out of the branching point P2, and L6 and L7 represent the signals lines branched out of the branching point P3. L2, L4, L6, and L7 are the terminal signal lines in this case; therefore, if the line widths thereof are W, and the current values are all the same, the sum of the current flowing through the signal lines L6 and L7 flows through the signal line L5. Consequently, the line width of this section is made 2W, the width of the signal line L3 W+2W=3W, and the width of the signal line L1 W+3W=4W. The current values of the terminal signal lines L4, L6, and L7 are not necessarily all equal; in this case, the current value of each signal line should be determined, and the line width is determined by obtaining the sum of respective current values with respect to the signal line of confluence.
申请公布号 JPS60140843(A) 申请公布日期 1985.07.25
申请号 JP19830248892 申请日期 1983.12.28
申请人 FUJITSU KK 发明人 TANIZAWA SATORU
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
代理机构 代理人
主权项
地址