| 摘要 |
PURPOSE:To speed up arithmetic processing by conducting both arithmetics based on the presence of carry of an operation element of the next stage simultaneously with another operation is started, and selecting either of them to apply sequentially the arithmetic processing. CONSTITUTION:LSI chips 10-0-10-n except the 1st stage chip 10-0 are provided with two operating devices 11(11-1-11-n) and 12(12-1-12-n) and with a multiplexer 13(13-1-13-n) selecting the arithmetic devices 11, 12 depending on the presence of the carry of the pre-stage chip 10-0. In the operating processing, the arithmetic of both devices 11-1, 12-1 of the next stage is conducted depending on the carry in advance at the same time when the arithmetic of, e.g., the chip 10-0 starts the arithmetic. When the arithmetic of the chip 10-0 is finished, the result is stored in a register 14-0 and also the multiplexer 13-1 of the chip 10-1 is operated in response to the presence of the carry, the result of both the devices 11-1 and 12-1 operated in advance is selected and it is stored in the register 14-1. The arithmetic is conducted sequentially similarly to attain high speed arithmetic processing. |
