| 摘要 |
A low capacitance pad structure is disclosed for testing a semiconductor chip, so as to enable the accurate measurement of rise times and delays in internal logic circuitry. The structure provides a capacitive coupling between the internal logic circuit under test and the capacitance of the probe connected to the input/output pad of the chip. This is achieved by inserting a coupling capacitance between the internal logic circuit and the input/output pad. The coupling capacitance is formed by providing a thin dielectric layer on top of an enlarged plate portion of the conductor line connected to the output of the internal logic circuit under test, so as to capacitively couple voltage swings on the line to a second level plate which forms the electrode to be contacted by the test probe. The capacitively coupled output pad enables the accurate characterization of the rise times and delay times of internal logic circuitry on an integrated circuit semiconductor chip, which would not be otherwise conveniently measurable. |
