发明名称 CONTROL METHOD OF PARTIAL WRITE TO SHARE MEMORY
摘要 PURPOSE:To solve easily and surely a problem of destruction of a new data in a share memory due to a special full write by suppressing the special full write when a write address belongs to a block copied to a buffer memory so as to process it as a partial write. CONSTITUTION:A processing unit (CPU) 1 has a buffer memory 2 and its address registration directory (BAA) 3 and the access request to a main memory is processed all by an access request control section (RQCTL) 4. Another processing unit (IOP) 100 is provided with an access request control section 11. When a write request from the IOP100 enters an access request buffer N (RQBFB) 21, a write request is received by a reception control circuit (PRI) 30 and the write to a main memory (MS) 50 is conducted in the said address. An address registration directory (FAA) 40 being a copy of the BAA3 as to the address is referenced and when its address exists in the FAA40, the block registration is made ineffective and the registration of the said block in the BA3 is cancelled.
申请公布号 JPS60140444(A) 申请公布日期 1985.07.25
申请号 JP19830245489 申请日期 1983.12.28
申请人 HITACHI SEISAKUSHO KK 发明人 SUMIMOTO TSUTOMU;KATOU MASAO
分类号 G06F12/08;G06F12/04 主分类号 G06F12/08
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