发明名称 DECIMAL NOTATION MULTIPLIER SYSTEM
摘要 PURPOSE:To shorten the operating time by processing an outer loop for line shift and an inner loop for additional/substraction as a series of operation so as to mix a multiplicand and an intermediate product in one register. CONSTITUTION:A decimal notation multiplier has a register A storing a multiplier and an intermediate product, a register B storing a multiplicand, a decimal adder/subtractor 1, a pre-shifter 2 having an algebracis shift right function of decimal ''1'' digit, a multiplier decoder extracting one digit of the multiplier from the low-order of the register A through a line 10 for the purpose of operation control and a gate 4 zeroing an output of the register B. Moreover, the multiplicand is stored while being shifted left by the number of effective digits of the multiplier after the sign is eliminated. Then the register A is used in common for the intermediate product, the pre-shifter 2 is made effective by the 1st addition/subtraction of each digit by the pre-shifter 2 and the addition/subtraction of each digit twice is conducted by making the pre-shifter 2 ineffective.
申请公布号 JPS60140429(A) 申请公布日期 1985.07.25
申请号 JP19830246929 申请日期 1983.12.28
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAOKA AKIRA;WADA KENICHI;KURIYAMA KAZUNORI
分类号 G06F7/496;G06F7/491;G06F7/508;G06F7/52;G06F7/527 主分类号 G06F7/496
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