发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent malfunction of a circuit of the next stage from taking place by connecting a clamp element clamping a logical level of an output circuit to an input terminal of an output element, connecting the clamp element to an output terminal of the output element and connecting a reference level wire giving a reference level of the clamp to the clamp element. CONSTITUTION:When other (n-1)-set of output circuits are inverted from a high level to a low level at the same time while a low level is outputted to an output circuit 1, a potential rise of DELTAVgnD(MAX)=(n-1).Ldi/dt is generated to a GND line to which emitters of output transistors (TRs) Q14-Qn4 are connected in common the same as a conventional circuit. The potential rise of the GND line increases a base potential of the output TRQ14 of the output circuit 1 to a potential of nearly same degree and further up to a collector potential, but the operation suppressing automatically the said collector potential rise is conducted by the operation of a clamp TRQA1. Thus, the level of the Vp1 does not surpass the threshold voltage of the circuit of the next stage, thereby preventing malfunction from taking place.
申请公布号 JPS60140925(A) 申请公布日期 1985.07.25
申请号 JP19830250113 申请日期 1983.12.27
申请人 NIPPON DENKI KK 发明人 KIYOZUKA NOBORU
分类号 H03K19/003 主分类号 H03K19/003
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