| 摘要 |
PURPOSE:To improve the performance of the entire titled system by storing an address and a data from a processor to a memory buffer, and releasing the common bus before the start of a memory operation to improve the utilizing efficiency of a common bus. CONSTITUTION:The processor receiving a reception signal 13 transmits an address to a common address bus 5. If it is a write request, a write data is outputted to a common data bus 4 at the same time, a write command is transmitted to a command line 16. These commands are fed to a bus control section 11 to inhibit the succeeding reception signal (13) transmission. The command controls a buffer control section 10 that the data and address on the common buses 4, 5 are fetched in a register of a memory buffer 6 in the clock timing 15. |
