| 摘要 |
Detector circuit transistors TL1, TL2 detect read currents Is1, Is2 from memory cells (one cell shown includes transistors TC1, TC2, resistors RL and diode R1) for delivery to inputs of a sense amplifier SA.
<??>The bases of transistors TL1, TL2 are crossconnected to provide a hysteresis characteristic when a current I1 is supplied by hysteresis control circuit HC.
<??>Current I1 is supplied when the potential on line Vwc is less than a predetermined potential Vrs.
<??>The potential on line Vwc is the logical sum of the potentials on driving word lines Vws, Vwn.
<??>In an address undecided region during address changeover the potentials on word lines Vws, Vwn are all less than Vrs, current I1 is supplied, and the hysteresis characteristic holds the inputs to sense amplifier SA in their previous state so that equal inputs are not applied.
<??>When the new address is decided a word line potential exceeds Vrs, the hysteresis characteristic is removed, and inputs to sense amp SA can change rapidly. |
