| 摘要 |
PURPOSE:To attain the transfer of data at a high speed between systems which work with different clocks by using a control means to a system to inform the propriety for transmission/reception of data and to control the transfer of data. CONSTITUTION:The output Q' of the 1st DFF is inverted by a shift-in S1. At the same time, the output Q is also inverted and therefore the output of an AND circuit 25 is inverted to 1 from 0. Then a negative pulse is produced from a pulse generating circuit 26 after a fixed period of time. The 1st and 2nd FF23 and 24 are cleared and preset by said negative pulse. Thus an input ready IR and an output ready OR are inverted from 0 to 1 and from 1 to 0 respectively. At the same time, the negative pulse is applied to a register group 22 via an NOT circuit 27 and therefore the data of a register group 21 is transferred to the group 22. In such a state where the data is held only in the group 21, a receivable state is informed to the 1st system 1. While a transmittable state is informed to the 2nd system 3.
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