发明名称 ARRAY LOGIC CIRCUIT
摘要 PURPOSE:To enable a user to select and decide an input circuit and an output circuit connected between plural terminals and word lines of an array part for each terminal, by forming a breaking part or a short-circuiting part at a proper area. CONSTITUTION:Plural bit lines 3 are provided together with word lines 11 and 12 which can be used for both input and output lines crossing the lines 3 and an input circuit 4, an output circuit 6, etc. connected to lines 11 and 12. Furthermore, the breaking or short-circuiting parts 20-25 consisting of fuses, transistors, etc. are formed among terminals 30-35 serving as input or output terminals, the circuits 4 and 6 corresponding to these terminals, a buffer 9 and lines 11 and 12 respectively. Those parts 20-25 are connected to a breaking or short- circuiting circuit 10. In such constitution, a user can select and decide the input and output circuits connected between plural terminals and word lines of an array part for each terminal.
申请公布号 JPS60139023(A) 申请公布日期 1985.07.23
申请号 JP19830249313 申请日期 1983.12.27
申请人 FUJITSU KK 发明人 YAMAGUCHI DAISUKE
分类号 H03K19/177 主分类号 H03K19/177
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