Digital phase lock loop system

摘要

A macro phase detector responds to large phase deviation between a locally generated signal and a reference signal for actuating a successive frequency approximation register to effect major count alteration in a counter for controlling a digital-to-analog converter and, in turn, a voltage controlled oscillator. Small phase error is detected by a phase detector, averaged, and employed to alter the count in the counter for introducing sensitive frequency adjustment. A second counter is clocked by the phase detector at one half the rate of the first counter and is used to update the first counter each time the phase difference reverses polarity. Loss of reference signal activates a detector for freezing the count in the counter to maintain frequency and phase within the accuracy of the controlled oscillator.