| 摘要 |
<p>PURPOSE:To decrease the circuit scale and also the delay time by using logical constitution so as to attain address conversion. CONSTITUTION:The high-order 2-bit of an address of 6-bit on row address lines LC of (m+1) lines, e.g., 6 lines, and the high-order 3-bit of the address of 6-bit on column address line LR of (n+1) lines, e.g., 6 lines, are converted into the address of 4-bit by a decoder of logical constitution, the result is used as the high- order bit and the remaining address is used as the low-order bit and then the address of 12-bit is converted into an address of 11-bit. In this case, since the address converting decoder is not constituted with an adder and a multiplier but with the logical constitution, even if the number of rows and columns is increased, the circuit scale is not increased and the address converting circuit is of small circuit scale and the delay time is less.</p> |
