| 摘要 |
PURPOSE:To change the performance of a processor according to a program stored in a memory by varying the transmission timing of an answer signal to the processor in accordance with a memory block to which an access request is given. CONSTITUTION:An answer signal RDY control circuit 1 sends a RDY signal corresponding to the access time of a memory to which an access is sent back to a CPU2 against a processor request PRQ signal given from the CPU2. In other words, the period during which the signal PRQ is produced and the signal RDY is sent back is changed dynamically in response to an access address. Therefore a memory block 4 can be formed with memory blocks 4a and 4b having different access times. For instance, a program requiring the high-speed processing and a program having no inconvenience with the low-speed processing are stored to the memory 4a of high cost and the memory 4b of low cost respectively. As a result, the performance of a processor can be changed according to the program stored in the memory. |
