| 摘要 |
PURPOSE:To prevent digital communication equipment from malfunctioning during system switching by controlling a clock with multiframe pulses for system switching from an FF which is set and reset with multiframe pulses of an in-use and a stand-by system. CONSTITUTION:Clocks C and C' from in-use and stand-by clock sources 8 and 9 which have clock generators 10 and 12 and multiframe pulse generating circuits 11 and 13 are inputted to a clock signal selector 14. Multiframe pulses 1 and 2 from the circuits 11 and 13 are inputted to a multiframe selector 15. When a system switching indication input 16 is supplied externally, a multiframe pulse generating circuit 17 for system switching composed of the FF which is set with the pulse 1 to generate a multiframe pulse 18 for system switching and reset with the pulse 2. When the signal 16 is supplied at a point 29 of time, the pulse 18 is generated with the pulse 1 and pulses 2 having the same intervals 5 and 7 before and after switching are sent out; and the transmission of clocks C and C' is stopped through a gate 19 with the pulse 18 during the system switching period 27. |
