发明名称 MICROPROGRAM CONTROL SYSTEM
摘要 PURPOSE:To eliminate delay defects at a setup time to perform operation of a computer in a high speed by indicating the end of an instruction with the last micro instruction but one to give a margin to setup of the next instruction. CONSTITUTION:The field of the micro instruction indicating the end of an instruction is called ERDY and consists of 2 bits. If the ERDY code is ''01'', an instruction setup indicating signal 9 is issued through an AND circuit 25 and an OR circuit 26 when a signal EX and a condition TEST are established and the output of a gate 23 is ''1''. If the ERDY code is ''10'', an AND circuit 24 is established and the setup indicating signal 9 is issued when the signal EX and the condition TEST are not established and the inverted output of the gate 23 is ''1''. If the ERDY code is ''11'', the AND circuit 24 is established when the condition TEST is not established and the AND circuit 25 is established when the condition TEST is established; and thus, the instruction setup indicating signal 9 is issued in any case.
申请公布号 JPS60134935(A) 申请公布日期 1985.07.18
申请号 JP19830241943 申请日期 1983.12.23
申请人 HITACHI SEISAKUSHO KK 发明人 NISHIYAMA TAKAAKI;HASHIMOTO MASAHIRO
分类号 G06F9/28;G06F9/22;G06F9/38 主分类号 G06F9/28
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