| 摘要 |
PURPOSE:To reduce load to main memory by providing guard elements with instructions to load adjoining data and inter-vector elements shift instructions when vector data are loaded from main memory to a vector register. CONSTITUTION:A vector processing unit consists of a vector instruction control circuit C5, a vector referring control circuit C6, a vector address circuit C7, a vector register control circuit C8, etc. The control circuit C8 holds the i-th vector retister VRi, and its main part consists of N pieces of R7i. The register VRi is provided with guard elements R7i1 and R7i2 which can hold numeric elements. When vector data are loaded from main memory to the vector register VRi, instructions to load adjoining data and shift instructions between vector elements are provided for the guard elements; therefore data once etched from the main memory become available for effective use, and a load to the main memory can be reduced. |
