| 摘要 |
PURPOSE:To accelerate extended vector operation by comparing respective elements of an operand counter, an address register and a vector and by providing a control circuit to renew a counter and a register independently. CONSTITUTION:When instruction words from a main memory unit 90 are stored in an instruction word register 10, an instruction decoding circuit 11 discriminates types of instructions. In case of scalar instructions, a scalar arithmetic unit 93 is activated, and in case of vector instructions, an order control circuit 12 is activated. Simultaneously, the contents of a general purpose register group 13 are transmitted to an extended vector arithmetic unit 100. The order control circuit 12 transmits one-cycle of start signals to the extended vector unit 100, and the next cycle continues transmission of a ''merge sort instruction valid'' signal. After the extended vector arithmetic operation has been completed, the contents of a top pre-operated element address (three pairs of elements) of each operand and operated elements (three pairs) are written back in registers (six units) which lower ranked four bits of the instruction word register 10 specify.
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